Field
This disclosure relates generally to process integration, and more specifically, to a method for integrating non-volatile memory cells with static random access memory cells and logic transistors.
Related Art
Many semiconductor devices include, or embed, non-volatile memory (NVM) cells with other transistor types on the same integrated circuit (IC). The manufacturing processes for the different transistor types may not be the same, requiring that the processes be integrated. For example, to integrate NVM with, for example, CMOS (complementary metal oxide semiconductor), the CMOS process may be modified to include the process steps necessary to fabricate the NVM memory cell and the supporting devices.
Non-volatile memory is commonly embedded in, for example, system-on-a-chip (SoC) integrated circuits having CMOS logic circuitry. The NVM may include a floating gate comprising polysilicon, or use a charge storage layer comprising nanocrystals, silicon nitride, or silicon oxynitride layer. The non-volatile memory cell may be integrated with various types of CMOS transistors used in analog and digital circuitry, such as for example, logic, high voltage switching transistors, drivers, or static random access memory (SRAM) cells.
The integration for NVM cells with logic transistors can be a challenge due to the different requirements for the NVM cells, which store charge, and the logic transistors which are commonly intended for high speed operation. The need for a charge storage layer in the NVM cell makes integration of the NVM cells and the logic transistors difficult, especially when various types of logic transistors are required.
Integration of NVM with logic transistors introduces additional wet etches, anneals, oxidations, etc. which modify the logic well profiles and the boundary between active and trench regions (trench fill recess, active corner rounding, etc). As a result, the logic devices no longer match the electrical targets of the original baseline process. Many learning cycles are needed to adjust the implants, etc. to approximate the original logic behavior, and ultimately it is not possible to exactly match the original targets/models. Consequently, the logic transistor manufacturing process needs to be re-characterized to work in the NVM-integrated flow.
Therefore, a need exists for a process integration flow that solves the above problems.